A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers
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The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unity-gain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12 b pipelined ADC is implemented in 65 nm CMOS that achieves 67.0 dB SNDR at 250 MS/s and consumes 49.7 mW of power from a 1.2 V power supply.
Date issued
2015-12Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
IEEE Journal of Solid-State Circuits
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Boo, Hyun H., Duane S. Boning, and Hae-Seung Lee. "A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers." IEEE Journal of Solid-State Circuits 50:12 (2015), p.2912-2921.
Version: Author's final manuscript
Other identifiers
INSPEC Accession Number: 15618350
ISSN
0018-9200
1558-173X