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A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers

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dc.contributor.author Boo, Hyun Ho
dc.contributor.author Boning, Duane S.
dc.contributor.author Lee, Hae-Seung
dc.date.accessioned 2016-06-08T20:05:00Z
dc.date.available 2016-06-08T20:05:00Z
dc.date.issued 2015-12
dc.date.submitted 2015-06
dc.identifier.issn 0018-9200
dc.identifier.issn 1558-173X
dc.identifier.other INSPEC Accession Number: 15618350
dc.identifier.uri http://hdl.handle.net/1721.1/103067
dc.description.abstract The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unity-gain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12 b pipelined ADC is implemented in 65 nm CMOS that achieves 67.0 dB SNDR at 250 MS/s and consumes 49.7 mW of power from a 1.2 V power supply. en_US
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en_US
dc.relation.isversionof http://dx.doi.org/10.1109/JSSC.2015.2467183 en_US
dc.rights Creative Commons Attribution-Noncommercial-Share Alike en_US
dc.rights.uri http://creativecommons.org/licenses/by-nc-sa/4.0/ en_US
dc.source Prof. Duane Boning en_US
dc.title A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers en_US
dc.type Article en_US
dc.identifier.citation Boo, Hyun H., Duane S. Boning, and Hae-Seung Lee. "A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers." IEEE Journal of Solid-State Circuits 50:12 (2015), p.2912-2921. en_US
dc.contributor.department Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science en_US
dc.contributor.approver Boning, Duane S. en_US
dc.contributor.mitauthor Boo, Hyun Ho en_US
dc.contributor.mitauthor Boning, Duane S. en_US
dc.contributor.mitauthor Lee, Hae-Seung en_US
dc.relation.journal IEEE Journal of Solid-State Circuits en_US
dc.identifier.mitlicense OPEN_ACCESS_POLICY en_US
dc.eprint.version Author's final manuscript en_US
dc.type.uri http://purl.org/eprint/type/JournalArticle en_US
eprint.status http://purl.org/eprint/status/PeerReviewed en_US
dspace.orderedauthors Boo, Hyun H.; Boning, Duane S.; Lee, Hae-Seung en_US
dspace.embargo.terms N en_US
dc.identifier.orcid https://orcid.org/0000-0002-7783-0403
dc.identifier.orcid https://orcid.org/0000-0002-0417-445X


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