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dc.contributor.authorShim, Keun Sup
dc.contributor.authorLis, Mieszko
dc.contributor.authorKhan, Omer
dc.contributor.authorDevadas, Srinivas
dc.date.accessioned2017-04-13T18:50:13Z
dc.date.available2017-04-13T18:50:13Z
dc.date.issued2015-09
dc.identifier.issn0018-9162
dc.identifier.issn1558-0814
dc.identifier.urihttp://hdl.handle.net/1721.1/108136
dc.description.abstractFor certain applications involving chip multiprocessors with more than 16 cores, a directoryless architecture with fine-grained and partial-context thread migration can outperform directory-based coherence, providing lighter on-chip traffic and reduced verification complexity.en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/MC.2015.263en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceProf. Devadas via Phoebe Ayresen_US
dc.titleThe Execution Migration Machine: Directoryless Shared-Memory Architectureen_US
dc.typeArticleen_US
dc.identifier.citationShim, Keun Sup; Lis, Mieszko; Khan, Omer and Devadas, Srinivas “The Execution Migration Machine: Directoryless Shared-Memory Architecture.” Computer 48, no. 9 (September 2015): 50–59. © 2015 Institute of Electrical and Electronics Engineers (IEEE)en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverDevadas, Srinivasen_US
dc.contributor.mitauthorShim, Keun Sup
dc.contributor.mitauthorLis, Mieszko
dc.contributor.mitauthorDevadas, Srinivas
dc.relation.journalComputeren_US
dc.eprint.versionOriginal manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsShim, Keun Sup; Lis, Mieszko; Khan, Omer; Devadas, Srinivasen_US
dspace.embargo.termsNen_US
dc.identifier.orcidhttps://orcid.org/0000-0001-8253-7714
mit.licenseOPEN_ACCESS_POLICYen_US


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