Packet Transactions: High-Level Programming for Line-Rate Switches
Author(s)Cheung, Alvin; Budiu, Mihai; Kim, Changhoon; Varghese, George; McKeown, Nick; Licking, Steve; Sivaraman Kaushalram, Anirudh; Balakrishnan, Hari; Alizadeh Attar, Mohammadreza; ... Show more Show less
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Many algorithms for congestion control, scheduling, network measurement, active queue management, and traffic engineering require custom processing of packets in the data plane of a network switch. To run at line rate, these data-plane algorithms must be implemented in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chips. The key challenge is that many data-plane algorithms create and modify algorithmic state. To achieve line-rate programmability for stateful algorithms, we introduce the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated chip-area overhead.
DepartmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Proceedings of the 2016 Conference on ACM SIGCOMM 2016 Conference - SIGCOMM '16
Association for Computing Machinery (ACM)
Sivaraman, Anirudh et al. “Packet Transactions: High-Level Programming for Line-Rate Switches.” 2016 ACM SIGCOMM Conference, Florianopolis, Brazil, 22-26 August, 2016. ACM Press, 2016, pp. 15–28.
Author's final manuscript