dc.contributor.author | Cheung, Alvin | |
dc.contributor.author | Budiu, Mihai | |
dc.contributor.author | Kim, Changhoon | |
dc.contributor.author | Varghese, George | |
dc.contributor.author | McKeown, Nick | |
dc.contributor.author | Licking, Steve | |
dc.contributor.author | Sivaraman Kaushalram, Anirudh | |
dc.contributor.author | Balakrishnan, Hari | |
dc.contributor.author | Alizadeh Attar, Mohammadreza | |
dc.date.accessioned | 2017-07-20T20:01:49Z | |
dc.date.available | 2017-07-20T20:01:49Z | |
dc.date.issued | 2016-08 | |
dc.identifier.isbn | 978-1-4503-4193-6 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/110792 | |
dc.description.abstract | Many algorithms for congestion control, scheduling, network measurement, active queue management, and traffic engineering require custom processing of packets in the data plane of a network switch. To run at line rate, these data-plane algorithms must be implemented in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built.
This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chips. The key challenge is that many data-plane algorithms create and modify algorithmic state. To achieve line-rate programmability for stateful algorithms, we introduce the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks.
We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated chip-area overhead. | en_US |
dc.description.sponsorship | National Science Foundation (U.S.) (CNS- 1563826) | en_US |
dc.description.sponsorship | National Science Foundation (U.S.) (CNS-1563788) | en_US |
dc.language.iso | en_US | |
dc.publisher | Association for Computing Machinery (ACM) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1145/2934872.2934900 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Other univ. web domain | en_US |
dc.title | Packet Transactions: High-Level Programming for Line-Rate Switches | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Sivaraman, Anirudh et al. “Packet Transactions: High-Level Programming for Line-Rate Switches.” 2016 ACM SIGCOMM Conference, Florianopolis, Brazil, 22-26 August, 2016. ACM Press, 2016, pp. 15–28. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.mitauthor | Sivaraman Kaushalram, Anirudh | |
dc.contributor.mitauthor | Balakrishnan, Hari | |
dc.contributor.mitauthor | Alizadeh Attar, Mohammadreza | |
dc.relation.journal | Proceedings of the 2016 Conference on ACM SIGCOMM 2016 Conference - SIGCOMM '16 | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dspace.orderedauthors | Sivaraman, Anirudh; Cheung, Alvin; Budiu, Mihai; Kim, Changhoon; Alizadeh, Mohammad; Balakrishnan, Hari; Varghese, George; McKeown, Nick; Licking, Steve | en_US |
dspace.embargo.terms | N | en_US |
dc.identifier.orcid | https://orcid.org/0000-0003-4034-0918 | |
dc.identifier.orcid | https://orcid.org/0000-0002-1455-9652 | |
dc.identifier.orcid | https://orcid.org/0000-0002-0014-6742 | |
mit.license | OPEN_ACCESS_POLICY | en_US |
mit.metadata.status | Complete | |