dc.contributor.author | Chowdhury, Nadim | |
dc.contributor.author | Antoniadis, Dimitri A. | |
dc.contributor.author | Palacios, Tomas | |
dc.date.accessioned | 2019-07-10T17:22:07Z | |
dc.date.available | 2019-07-10T17:22:07Z | |
dc.date.issued | 2017-05 | |
dc.identifier.issn | 0741-3106 | |
dc.identifier.issn | 1558-0563 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/121568 | |
dc.description.abstract | We study the performance of GaN nanowire n-MOSFETs (GaN-NW-nFETs) with a channel length, Lg = 5 nm based on fully ballistic quantum transport simulations. Our simulation results show high ION = 1137μA/μm and excellent on-off characteristics with Q = gm/SS = 188 μS-decade/μm-mV calculated for Ioff = 1 nA/μm and VGS = VDS = VCC = 0.5 V. These results represent: 1) ∼ 15% higher Ion than Si-NW-nFET and 2) ∼ 17% better Q than Si-NW-nFET, all with Lg = 5 nm, thus suggesting the GaN n-channel, an intriguing option for application in logic at sub-10-nm channel length. The superior performance of the GaN channel compared with Si and other semiconductors at this scaled dimension can be attributed to its relatively higher effective mass of electron and lower permittivity. | en_US |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | 10.1109/LED.2017.2703953 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Other repository | en_US |
dc.title | GaN Nanowire n-MOSFET with 5 nm Channel Length for Applications in Digital Electronics | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Chowdhury, Nadim, Giuseppe Iannaccone, Gianluca Fiori, Dimitri A. Antoniadis and Tomás Palacios. "GaN Nanowire n-MOSFET with 5 nm Channel Length for Applications in Digital Electronics." Electron Device Letters 38, issue 7 (July 2017): pp. 859 - 862. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Microsystems Technology Laboratories | en_US |
dc.relation.journal | Electron Device Letters | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dc.date.updated | 2019-07-01T12:39:55Z | |
dspace.date.submission | 2019-07-01T12:39:59Z | |
mit.journal.volume | 38 | en_US |
mit.journal.issue | 7 | en_US |