dc.contributor.author | Lu, Wenjie | |
dc.contributor.author | Zhao, Xin | |
dc.contributor.author | Choi, Dongsung | |
dc.contributor.author | El Kazzi, Salim | |
dc.contributor.author | del Alamo, Jesus A | |
dc.date.accessioned | 2020-07-14T21:41:19Z | |
dc.date.available | 2020-07-14T21:41:19Z | |
dc.date.issued | 2017-04 | |
dc.identifier.issn | 0741-3106 | |
dc.identifier.issn | 1558-0563 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/126190 | |
dc.description.abstract | This letter introduces a novel alcohol-based digital etch technique for III-V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at V DS = 50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides. | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/led.2017.2690598 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Prof. del Alamo via Phoebe Ayers | en_US |
dc.title | Alcohol-Based Digital Etch for III–V Vertical Nanowires With Sub-10 nm Diameter | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Lu, Wenjie et al. "Alcohol-Based Digital Etch for III–V Vertical Nanowires With Sub-10 nm Diameter." IEEE Electron Device Letters 38, 5 (May 2017): 548 - 551 © 2017 IEEE | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Microsystems Technology Laboratories | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.relation.journal | IEEE Electron Device Letters | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dspace.date.submission | 2020-07-10T18:25:56Z | |
mit.journal.volume | 38 | en_US |
mit.journal.issue | 5 | en_US |
mit.license | OPEN_ACCESS_POLICY | |
mit.metadata.status | Complete | |