| dc.contributor.author | Vardi, Alon | |
| dc.contributor.author | Kong, Lisa (Lisa Fanzhen) | |
| dc.contributor.author | Lu, Wenjie | |
| dc.contributor.author | Cai, Xiaowei | |
| dc.contributor.author | Zhao, Xin | |
| dc.contributor.author | Grajal de la Fuente, Jesus | |
| dc.contributor.author | del Alamo, Jesus A | |
| dc.date.accessioned | 2020-07-15T14:24:58Z | |
| dc.date.available | 2020-07-15T14:24:58Z | |
| dc.date.issued | 2018-01 | |
| dc.date.submitted | 2017-12 | |
| dc.identifier.isbn | 9781538635599 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/126197 | |
| dc.description.abstract | We demonstrate self-aligned InGaAs FinFETs with fin widths down to 5 nm fabricated through a CMOS compatible front-end process. Precision dry etching of the recess cap results in metal contacts that are about 5 nm away from the intrinsic portion of the fin. The new process has allowed us to fabricate devices with undoped fins and compare them with delta-doped fins. We find that in highly scaled transistors, undoped fin devices show better OFF-state and a tighter VT distribution but similar ON-state characteristics, as compared with δ-doped-fin transistors. 2D Poisson-Schrodinger simulations reveal undoped fins making more effective use of the fin height. | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
| dc.relation.isversionof | http://dx.doi.org/10.1109/iedm.2017.8268411 | en_US |
| dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
| dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
| dc.source | Prof. del Alamo via Phoebe Ayers | en_US |
| dc.title | Self-aligned InGaAs FinFETs with 5-nm fin-width and 5-nm gate-contact separation | en_US |
| dc.type | Article | en_US |
| dc.identifier.citation | Vardi, Alon et al. "Self-aligned InGaAs FinFETs with 5-nm fin-width and 5-nm gate-contact separation." IEEE International Electron Devices Meeting (IEDM), December 2017, San Francisco, CA, USA, Institute of Electrical and Electronics Engineers, January 2018 © 2017 IEEE | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Microsystems Technology Laboratories | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
| dc.relation.journal | IEEE International Electron Devices Meeting (IEDM) | en_US |
| dc.eprint.version | Author's final manuscript | en_US |
| dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
| eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
| dspace.date.submission | 2020-07-10T18:20:52Z | |
| mit.license | OPEN_ACCESS_POLICY | |
| mit.metadata.status | Complete | |