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Author restrospective AEGIS: architecture for tamper-evident and tamper-resistant processing
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AEGIS is a single-chip secure processor that can be used to protect the integrity and confidentiality of an application program from both physical and software attacks. We briefly describe the history behind this architecture and its key features, discuss main observations and lessons from the project, and list limitations of AEGIS and how recent research addresses them.
Date issued
2014Department
Massachusetts Institute of Technology. Computer Science and Artificial Intelligence LaboratoryPublisher
Association for Computing Machinery (ACM)
Citation
Suh, G. Edward, Fletcher, Christopher, Clarke, Dwaine, Gassend, Blaise, van Dijk, Marten et al. 2014. "Author restrospective AEGIS: architecture for tamper-evident and tamper-resistant processing."
Version: Author's final manuscript