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dc.contributor.authorSuh, G. Edward
dc.contributor.authorFletcher, Christopher
dc.contributor.authorClarke, Dwaine
dc.contributor.authorGassend, Blaise
dc.contributor.authorvan Dijk, Marten
dc.contributor.authorDevadas, Srinivas
dc.date.accessioned2021-11-24T19:05:39Z
dc.date.available2021-11-05T16:42:03Z
dc.date.available2021-11-24T19:05:39Z
dc.date.issued2014
dc.identifier.urihttps://hdl.handle.net/1721.1/137542.2
dc.description.abstractAEGIS is a single-chip secure processor that can be used to protect the integrity and confidentiality of an application program from both physical and software attacks. We briefly describe the history behind this architecture and its key features, discuss main observations and lessons from the project, and list limitations of AEGIS and how recent research addresses them.en_US
dc.language.isoen
dc.publisherAssociation for Computing Machinery (ACM)en_US
dc.relation.isversionof10.1145/2591635.2591665en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT web domainen_US
dc.titleAuthor restrospective AEGIS: architecture for tamper-evident and tamper-resistant processingen_US
dc.typeArticleen_US
dc.identifier.citationSuh, G. Edward, Fletcher, Christopher, Clarke, Dwaine, Gassend, Blaise, van Dijk, Marten et al. 2014. "Author restrospective AEGIS: architecture for tamper-evident and tamper-resistant processing."en_US
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratoryen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dc.date.updated2019-05-28T16:00:44Z
dspace.date.submission2019-05-28T16:00:45Z
mit.metadata.statusPublication Information Neededen_US


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