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A Multi-process Design of Paging System

Author(s)
Huber, Andrew R.
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DownloadMIT-LCS-TR-171.pdf (5.092Mb)
Advisor
Clark, David D.
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Abstract
This thesis presents a design for a paging system that may be used to implement a virtual memory on a large scale, demand paged computer utility. A model for such a computer system with a multi-level, hierarchical memory system is presented. The functional requirements of a paging system for such a model are discussed, with emphasis on the parallelism inherent in the algorithms used to implement the memory management functions.
Date issued
1976-12
URI
https://hdl.handle.net/1721.1/149465
Series/Report no.
MIT-LCS-TR-171

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  • LCS Technical Reports (1974 - 2003)

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