A Multi-process Design of Paging System
| dc.contributor.advisor | Clark, David D. | en_US |
| dc.contributor.author | Huber, Andrew R. | en_US |
| dc.date.accessioned | 2023-03-29T15:00:48Z | |
| dc.date.available | 2023-03-29T15:00:48Z | |
| dc.date.issued | 1976-12 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149465 | |
| dc.description.abstract | This thesis presents a design for a paging system that may be used to implement a virtual memory on a large scale, demand paged computer utility. A model for such a computer system with a multi-level, hierarchical memory system is presented. The functional requirements of a paging system for such a model are discussed, with emphasis on the parallelism inherent in the algorithms used to implement the memory management functions. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-171 | |
| dc.title | A Multi-process Design of Paging System | en_US |
| dc.identifier.oclc | 03222488 |
