Fault Tolerance in Packet Communication Computer Archiectures
| dc.contributor.advisor | Dennis, Jack B. | en_US |
| dc.contributor.author | Leung, Clement Kin Cho | en_US |
| dc.date.accessioned | 2023-03-29T15:04:51Z | |
| dc.date.available | 2023-03-29T15:04:51Z | |
| dc.date.issued | 1980-12 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149531 | |
| dc.description.abstract | It is attractive to implement a large scale parallel processing system as a self-timed hardware system with decentralized control and to improve maintainability and availability in such a system through fault tolerance. In this thesis we show how to tolerate hardware failures in a self-timed hardware system with a packet communication architecture, designed to execute parallel programs organized by data flow concepts. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-250 | |
| dc.title | Fault Tolerance in Packet Communication Computer Archiectures | en_US |
| dc.identifier.oclc | 7096129 |
