MIT Libraries logoDSpace@MIT

MIT
View Item 
  • DSpace@MIT Home
  • Computer Science and Artificial Intelligence Lab (CSAIL)
  • LCS Publications
  • LCS Technical Reports (1974 - 2003)
  • View Item
  • DSpace@MIT Home
  • Computer Science and Artificial Intelligence Lab (CSAIL)
  • LCS Publications
  • LCS Technical Reports (1974 - 2003)
  • View Item
JavaScript is disabled for your browser. Some features of this site may not work without it.

A Switch-level Simulation Model for Integrated Logic Circuits

Author(s)
Bryant, Randal Everitt
Thumbnail
DownloadMIT-LCS-TR-259.pdf (8.119Mb)
Advisor
Dennis, Jack B.
Metadata
Show full item record
Abstract
Switch-level simulators model a metal oxide semiconductor (MOS) large scale integrated (LSI) circuits as a network of transistor "switches". They can simulate many aspects of MOS circuits which cannot be expressed in the Boolean logic gate model, such as bidrecttional pass transistors, dynamic storage, and charge sharing.
Date issued
1981-03
URI
https://hdl.handle.net/1721.1/149539
Series/Report no.
MIT-LCS-TR-259

Collections
  • LCS Technical Reports (1974 - 2003)

Browse

All of DSpaceCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsThis CollectionBy Issue DateAuthorsTitlesSubjects

My Account

Login

Statistics

OA StatisticsStatistics by CountryStatistics by Department
MIT Libraries
PrivacyPermissionsAccessibilityContact us
MIT
Content created by the MIT Libraries, CC BY-NC unless otherwise noted. Notify us about copyright concerns.