The Impact of Layer Assignment Methods on Layout Algorithms for Integrated Circuits
| dc.contributor.advisor | Leiserson, Charles E. | en_US |
| dc.contributor.author | Pinter, Ron Yair | en_US |
| dc.date.accessioned | 2023-03-29T15:07:30Z | |
| dc.date.available | 2023-03-29T15:07:30Z | |
| dc.date.issued | 1983-08 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149569 | |
| dc.description.abstract | Programs for integrated circuit layout at the module assembly level are typically decomposed into two phases - placement and routing. In this thesis we investigate a third phase which is often implicitly assumed - layer assignment. This thesis studies how layer assignment methodologies interact with placement and routing. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-291 | |
| dc.title | The Impact of Layer Assignment Methods on Layout Algorithms for Integrated Circuits | en_US |
| dc.identifier.oclc | 10990081 |
