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dc.contributor.authorBhatt, Sandeep N.en_US
dc.date.accessioned2023-03-29T15:11:56Z
dc.date.available2023-03-29T15:11:56Z
dc.date.issued1984-02
dc.identifier.urihttps://hdl.handle.net/1721.1/149619
dc.description.abstractThis thesis is motivated by the need for a clearer understanding of various issues in VLSI layout. Within a formal setting, we identify critical properties of circuits that determine the quality of their layouts.en_US
dc.relation.ispartofseriesMIT-LCS-TR-351
dc.titleThe Complexity of Graph Layour and Channel Routing for VLSIen_US
dc.identifier.oclc16930313


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