Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation
| dc.contributor.advisor | Agarwal, Anant | en_US |
| dc.contributor.author | Babb, Jonathan William | en_US |
| dc.date.accessioned | 2023-03-29T15:20:52Z | |
| dc.date.available | 2023-03-29T15:20:52Z | |
| dc.date.issued | 1993-11 | |
| dc.identifier.uri | https://hdl.handle.net/1721.1/149751 | |
| dc.description.abstract | Existing FPGA-based logic emulators are limited by inter-chip communication bandwidth, resulting in low gate utilization (10 to 20 percent of usable gates). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. | en_US |
| dc.relation.ispartofseries | MIT-LCS-TR-586 | |
| dc.title | Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation | en_US |
