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Thermal Modeling and Device Noise Properties of Three-Dimensional-SOI Technology

Author(s)
Chen, Tze Wee; Chun, Jung-Hoon; Lu, Yi-Chang; Navid, Reza; Wang, Wei; Chen, Chang-Lee; Dutton, Robert W.; ... Show more Show less
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Abstract
Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-mum three-dimensional (3-D)-SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D-SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D-SOI technology are also characterized and compared with conventional bulk CMOS technology.
Date issued
2009-03
URI
http://hdl.handle.net/1721.1/52421
Department
Lincoln Laboratory
Journal
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers
Citation
Tze Wee Chen et al. “Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology.” Electron Devices, IEEE Transactions on 56.4 (2009): 656-664. © 2009 Institute of Electrical and Electronics Engineers
Version: Final published version
Other identifiers
INSPEC Accession Number: 10556018
ISSN
0018-9383
Keywords
three-dimensional (3-D) integrated circuit, thermal modeling, electrothermal, Device noise, 3-D silicon-on-insulator

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