Thermal Modeling and Device Noise Properties of Three-Dimensional-SOI Technology

Abstract

Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-mum three-dimensional (3-D)-SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D-SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D-SOI technology are also characterized and compared with conventional bulk CMOS technology.