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A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

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dc.contributor.author Kim, Byeong-Su
dc.contributor.author Liu, Yong
dc.contributor.author Dickson, Timothy O.
dc.contributor.author Bulzacchelli, John F.
dc.contributor.author Friedman, Daniel J.
dc.date.accessioned 2010-03-18T18:29:47Z
dc.date.available 2010-03-18T18:29:47Z
dc.date.issued 2009-12
dc.date.submitted 2009-06
dc.identifier.issn 0018-9200
dc.identifier.other INSPEC Accession Number: 11020424
dc.identifier.uri http://hdl.handle.net/1721.1/52716
dc.description.abstract A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is reported. Based on expected channel characteristics, the proposed I/O features low-impedance transmitter termination, high-impedance receiver termination, and a receiver with modified DFE with IIR filter feedback (DFE-IIR). The DFE-IIR receiver uses a single additional IIR filter feedback tap to compensate many post cursors without paying the power and area penalty that would be incurred with a conventional high tap-count DFE. Equalization capabilities of the compact I/O at 10 Gb/s are demonstrated over various channels including conventional chip-to-chip and backplane links with half-baud losses of up to 27 dB. Finally, a transmitter-receiver pair operating over a 40-mm on-chip emulated silicon carrier channel was demonstrated to 8.9 Gb/s, at a link power efficiency of 1.9 mW/Gb/s. en
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers en
dc.relation.isversionof http://dx.doi.org/10.1109/jssc.2009.2031015 en
dc.rights Article is made available in accordance with the publisher’s policy and may be subject to US copyright law. Please refer to the publisher’s site for terms of use. en
dc.source IEEE en
dc.subject backplane channel communication en
dc.subject chip-to-chip communication en
dc.subject compact I/O en
dc.subject continuous-time IIR filter en
dc.subject decision feedback equalizer en
dc.subject serial link en
dc.subject silicon carrier links en
dc.title A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS en
dc.type Article en
dc.identifier.citation Byungsub Kim et al. “A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS.” Solid-State Circuits, IEEE Journal of 44.12 (2009): 3526-3538. © 2009 Institute of Electrical and Electronics Engineers en
dc.contributor.department Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science en_US
dc.contributor.approver Kim, Byeong-Su
dc.contributor.mitauthor Kim, Byeong-Su
dc.relation.journal IEEE Journal of Solid-State Circuits en
dc.identifier.mitlicense PUBLISHER_POLICY en
dc.eprint.version Final published version en
dc.type.uri http://purl.org/eprint/type/JournalArticle en
eprint.status http://purl.org/eprint/status/PeerReviewed en
dspace.orderedauthors Kim, Byungsub; Liu, Yong; Dickson, Timothy O.; Bulzacchelli, John F.; Friedman, Daniel J. en


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