Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits
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In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 times 1024 diode array with 8-mum pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
Date issued
2009-10Department
Lincoln LaboratoryJournal
IEEE International Conference on 3D System Integration, 2009. 3DIC 2009.
Publisher
Institute of Electrical and Electronics Engineers
Citation
Chen, C.L. et al. "Wafer-Scale 3D Integration of InGaAs Image Sensors with Si Readout
Circuits." IEEE International Conference on 3D System Integration, 2009. 3DIC 2009. p.1-4. ©2009 Institute of Electrical and Electronics Engineers.
Version: Final published version
Other identifiers
INSPEC Accession Number: 10943264
ISBN
978-1-4244-4511-0
978-1-4244-4512-7