Towards nanoimprint lithography-aware layout design checking
Author(s)Boning, Duane S.; Taylor, Hayden Kingsley
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Just as the simulation of photolithography has enabled resolution-enhancement through Optical Proximity Correction, the physical simulation of nanoimprint lithography is needed to guide the design of products that will use this process. We present an extremely fast method for simulating thermal nanoimprint lithography. The technique encapsulates the resist's mechanical behavior using an analytical function for its surface deformation when loaded at a single location. It takes a discretized stamp design and finds resist and stamp deflections in a series of steps. We further accelerate the simulation of feature-rich patterns by pre-computing dimensionless relationships between the applied pressure, the resist's mechanical properties, and the residual layer thickness, for stamps patterned with uniform arrays of a variety of common feature shapes. The approach is fast enough to be used iteratively when selecting processing parameters and refining layouts. The approach is demonstrated in action with three nanoimprint test-patterns, and describes experimentally measured residual layer thickness variations to within 10-15% or better. Finally, our technique is used to propose nanoimprint-aware design rules.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology Laboratories
Proceedings of SPIE--the International Society for Optical Engineering ; v. 7641
Taylor, Hayden, and Duane Boning. “Towards nanoimprint lithography-aware layout design checking.” Design for Manufacturability through Design-Process Integration IV. Ed. Michael L. Rieger & Joerg Thiele. San Jose, California, USA: SPIE, 2010. 76410U-12. ©2010 SPIE.
Final published version