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dc.contributor.authorBoning, Duane S.
dc.contributor.authorTaylor, Hayden Kingsley
dc.date.accessioned2010-09-16T18:54:33Z
dc.date.available2010-09-16T18:54:33Z
dc.date.issued2010-04
dc.date.submitted2010-02
dc.identifier.issn0277-786X
dc.identifier.urihttp://hdl.handle.net/1721.1/58569
dc.description.abstractJust as the simulation of photolithography has enabled resolution-enhancement through Optical Proximity Correction, the physical simulation of nanoimprint lithography is needed to guide the design of products that will use this process. We present an extremely fast method for simulating thermal nanoimprint lithography. The technique encapsulates the resist's mechanical behavior using an analytical function for its surface deformation when loaded at a single location. It takes a discretized stamp design and finds resist and stamp deflections in a series of steps. We further accelerate the simulation of feature-rich patterns by pre-computing dimensionless relationships between the applied pressure, the resist's mechanical properties, and the residual layer thickness, for stamps patterned with uniform arrays of a variety of common feature shapes. The approach is fast enough to be used iteratively when selecting processing parameters and refining layouts. The approach is demonstrated in action with three nanoimprint test-patterns, and describes experimentally measured residual layer thickness variations to within 10-15% or better. Finally, our technique is used to propose nanoimprint-aware design rules.en_US
dc.language.isoen_US
dc.publisherSPIEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1117/12.846499en_US
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en_US
dc.sourceSPIEen_US
dc.titleTowards nanoimprint lithography-aware layout design checkingen_US
dc.typeArticleen_US
dc.identifier.citationTaylor, Hayden, and Duane Boning. “Towards nanoimprint lithography-aware layout design checking.” Design for Manufacturability through Design-Process Integration IV. Ed. Michael L. Rieger & Joerg Thiele. San Jose, California, USA: SPIE, 2010. 76410U-12. ©2010 SPIE.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.departmentMassachusetts Institute of Technology. Microsystems Technology Laboratoriesen_US
dc.contributor.approverBoning, Duane S.
dc.contributor.mitauthorBoning, Duane S.
dc.contributor.mitauthorTaylor, Hayden Kingsley
dc.relation.journalProceedings of SPIE--the International Society for Optical Engineering ; v. 7641en_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsTaylor, Hayden; Boning, Duaneen
dc.identifier.orcidhttps://orcid.org/0000-0002-0417-445X
mit.licensePUBLISHER_POLICYen_US
mit.metadata.statusComplete


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