A Low Temperature Fully Lithographic Process For Metal–Oxide Field-Effect Transistors
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We report a low temperature ( ~ 100à °C) lithographic method for fabricating hybrid metal oxide/organic field-effect transistors (FETs) that combine a zinc-indium-oxide (ZIO) semiconductor channel and organic, parylene, dielectric layer. The transistors show a field-effect mobility of (12à ±0.8) cm2 V-1 s-1, on/off ratio of 108 and turn-off voltage of Voff = -1 V. This work demonstrates that organic and inorganic layers can be deposited and patterned using a low temperature budget, integrated lithographic process to make FETs suitable for large area electronic applications.
Date issued
2009-12Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology LaboratoriesJournal
Journal of Display Technology
Publisher
Institute of Electrical and Electronics Engineers
Citation
Wang, A.; Yaglioglu, B.; Sodini, C.G.; Bulovic, V.; Akinwande, A.I.; , "A Low Temperature Fully Lithographic Process For Metal–Oxide Field-Effect Transistors," Display Technology, Journal of , vol.6, no.1, pp.22-26, Jan. 2010 © Copyright 2010 IEEE
Version: Final published version
ISSN
1551-319X
Keywords
integrated lithographic process, large area electronic applications, low temperature fully lithographic process, metal-oxide field-effect transistors, zinc-indium-oxide semiconductor channel, amorphous semiconductors, Thin-film transistors (TFTs)