Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Author(s)
Keast, Craig L.; Chen, Chang-Lee; Chen, Chenson K.; Yost, Donna-Ruth W.; Knecht, Jeffrey M.; ... Show more
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Abstract
RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved.
Date issued
2009-02
URI
http://hdl.handle.net/1721.1/58963
Department
Lincoln Laboratory
Journal
IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09
Publisher
Institute of Electrical and Electronics Engineers
Citation
Chen, C.L. et al. “Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers.” Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on. 2009. 1-4. © 2009 Institute of Electrical and Electronics Engineers.
Version: Final published version
ISBN
978-1-4244-3940-9
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