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dc.contributor.authorKeast, Craig L.
dc.contributor.authorChen, Chang-Lee
dc.contributor.authorChen, Chenson K.
dc.contributor.authorYost, Donna-Ruth W.
dc.contributor.authorKnecht, Jeffrey M.
dc.contributor.authorWyatt, Peter W.
dc.contributor.authorBurns, James A.
dc.contributor.authorWarner, Keith
dc.contributor.authorGouker, Pascale M.
dc.contributor.authorHealey, Paul D.
dc.contributor.authorWheeler, Bruce D.
dc.date.accessioned2010-10-08T14:28:37Z
dc.date.available2010-10-08T14:28:37Z
dc.date.issued2009-02
dc.date.submitted2009-01
dc.identifier.isbn978-1-4244-3940-9
dc.identifier.urihttp://hdl.handle.net/1721.1/58963
dc.description.abstractRF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved.en_US
dc.description.sponsorshipUnited States. Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002)en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/SMIC.2009.4770536en_US
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en_US
dc.sourceIEEEen_US
dc.titleWafer-scale 3D integration of silicon-on-insulator RF amplifiersen_US
dc.typeArticleen_US
dc.identifier.citationChen, C.L. et al. “Wafer-Scale 3D Integration of Silicon-on-Insulator RF Amplifiers.” Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on. 2009. 1-4. © 2009 Institute of Electrical and Electronics Engineers.en_US
dc.contributor.departmentLincoln Laboratoryen_US
dc.contributor.approverKeast, Craig L.
dc.contributor.mitauthorKeast, Craig L.
dc.contributor.mitauthorChen, Chang-Lee
dc.contributor.mitauthorChen, Chenson K.
dc.contributor.mitauthorYost, Donna-Ruth W.
dc.contributor.mitauthorKnecht, Jeffrey M.
dc.contributor.mitauthorWyatt, Peter W.
dc.contributor.mitauthorBurns, James A.
dc.contributor.mitauthorWarner, Keith
dc.contributor.mitauthorGouker, Pascale M.
dc.contributor.mitauthorHealey, Paul D.
dc.contributor.mitauthorWheeler, Bruce D.
dc.relation.journalIEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09en_US
dc.eprint.versionFinal published versionen_US
dc.identifier.pmidINSPEC Accession Number: 10468225
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsChen, C. L.; Chen, C. K.; Yost, D.-R.; Knecht, J. M.; Wyatt, P. W.; Burns, J. A.; Warner, K.; Gouker, P. M.; Healey, P.; Wheeler, B.; Keast, C. L.en
mit.licensePUBLISHER_POLICYen_US
mit.metadata.statusComplete


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