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dc.contributor.authorBrar, B.
dc.contributor.authorKim, D. H.
dc.contributor.authordel Alamo, Jesus A.
dc.contributor.authorAntoniadis, Dimitri A.
dc.date.accessioned2010-10-21T20:30:37Z
dc.date.available2010-10-21T20:30:37Z
dc.date.issued2010-03
dc.date.submitted2009-12
dc.identifier.isbn978-1-4244-5640-6
dc.identifier.isbn978-1-4244-5639-0
dc.identifier.otherINSPEC Accession Number: 11207312
dc.identifier.urihttp://hdl.handle.net/1721.1/59455
dc.description.abstractWe have experimentally extracted the virtual-source electron injection velocity, vx0, of various III-V HFETs at room temperature. This is the carrier velocity that matters for logic applications of these transistors. Sub-100 nm devices with mu n > 10,000 cm2/V-s exhibit vx0 in excess of 3 x 107 cm/s even at V[subscript DD] = 0.5 V. This is over 2 times that of state-of-the-art Si devices at V[subscript DD]> 1. We have verified our extraction methodology for vx0 by building a simple charge-based semi-empirical model for the I-V characteristics of III-V HFETs. This model yields an excellent description of the entire I-V characteristics of the devices from subthreshold to inversion and from linear to saturation regimes with fitted electron velocities that are very close to those independently obtained through our proposed extraction methodology.en_US
dc.description.sponsorshipIntel Corporationen_US
dc.description.sponsorshipSemiconductor Research Corporation. Center for Materials, Structures and Devicesen_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/IEDM.2009.5424268en_US
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en_US
dc.sourceIEEEen_US
dc.titleExtraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETsen_US
dc.typeArticleen_US
dc.identifier.citationKim, D.-H. et al. “Extraction of virtual-source injection velocity in sub-100 nm III–V HFETs.” Electron Devices Meeting (IEDM), 2009 IEEE International. 2009. 1-4. © 2010 Institute of Electrical and Electronics Engineers.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.departmentMassachusetts Institute of Technology. Microsystems Technology Laboratoriesen_US
dc.contributor.approverdel Alamo, Jesus A.
dc.contributor.mitauthorKim, D. H.
dc.contributor.mitauthordel Alamo, Jesus A.
dc.contributor.mitauthorAntoniadis, Dimitri A.
dc.relation.journal2009 IEEE International Electron Devices Meeting (IEDM)en_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsKim, D.-H.; del Alamo, J. A.; Antoniadis, D. A.; Brar, B.en
dc.identifier.orcidhttps://orcid.org/0000-0002-4836-6525
mit.licensePUBLISHER_POLICYen_US
mit.metadata.statusComplete


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