A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [Delta Sigma] ADC with VCO-based integrator and quantizer
DownloadPark-2009-A 0.13m CMOS 78dB SNDR 87mW 20MHz BW CT ADC with VCO-based integrator and quantizer.pdf (1.163Mb)
A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer
MetadataShow full item record
In this paper we demonstrate a new technique that eliminates the impact of K[subscript v] nonlinearity by preserving the integral relationship of the VCO output phase to the input signal. Leveraging the VCO output phase directly precludes the need to span the entire nonlinear K[subscript v] characteristic since small perturbations (in the range of 10s of mV) at the tuning node are sufficient to shift the VCO phase by a substantial amount. Since an open-loop VCO is sensitive to frequency offsets and drift, and easily saturates its phase detector for large input signals, some form of negative feedback is necessary. Here, a multibit DAC subtracts the previously quantized phase value from the VCO input, creating a residue that is integrated during the next clock cycle. This feedback loop not only allows large signals to drive the VCO without incurring distortion from K[subscript v] nonlinearity, but also it is a 1s,-order CT DeltaSigma ADC loop, and it therefore 1s,-order shapes quantization noise.
IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009
Institute of Electrical and Electronics Engineers
Park, M., and M. Perrott. “A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [DeltaSigma] ADC with VCO-based integrator and quantizer.” Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 170-171,171a. ©2009 IEEE.
Final published version
INSPEC Accession Number: 10727917