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A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [Delta Sigma] ADC with VCO-based integrator and quantizer

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dc.contributor.author Park, Matthew
dc.date.accessioned 2010-12-02T22:28:16Z
dc.date.available 2010-12-02T22:28:16Z
dc.date.issued 2009-05
dc.date.submitted 2009-02
dc.identifier.isbn 978-1-4244-3458-9
dc.identifier.other INSPEC Accession Number: 10727917
dc.identifier.uri http://hdl.handle.net/1721.1/60071
dc.description.abstract In this paper we demonstrate a new technique that eliminates the impact of K[subscript v] nonlinearity by preserving the integral relationship of the VCO output phase to the input signal. Leveraging the VCO output phase directly precludes the need to span the entire nonlinear K[subscript v] characteristic since small perturbations (in the range of 10s of mV) at the tuning node are sufficient to shift the VCO phase by a substantial amount. Since an open-loop VCO is sensitive to frequency offsets and drift, and easily saturates its phase detector for large input signals, some form of negative feedback is necessary. Here, a multibit DAC subtracts the previously quantized phase value from the VCO input, creating a residue that is integrated during the next clock cycle. This feedback loop not only allows large signals to drive the VCO without incurring distortion from K[subscript v] nonlinearity, but also it is a 1s,-order CT DeltaSigma ADC loop, and it therefore 1s,-order shapes quantization noise. en_US
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.relation.isversionof http://dx.doi.org/10.1109/ISSCC.2009.4977362 en_US
dc.rights Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. en_US
dc.source IEEE en_US
dc.title A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [Delta Sigma] ADC with VCO-based integrator and quantizer en_US
dc.title.alternative A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer en_US
dc.type Article en_US
dc.identifier.citation Park, M., and M. Perrott. “A 0.13[mu]m CMOS 78dB SNDR 87mW 20MHz BW CT [DeltaSigma] ADC with VCO-based integrator and quantizer.” Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 170-171,171a. ©2009 IEEE. en_US
dc.contributor.approver Perrott, Michael H.
dc.contributor.mitauthor Park, Matthew
dc.contributor.mitauthor Perrott, Michael H.
dc.contributor.mitauthor Perrott, Michael H.
dc.relation.journal IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009 en_US
dc.identifier.mitlicense PUBLISHER_POLICY en_US
dc.eprint.version Final published version en_US
dc.type.uri http://purl.org/eprint/type/ConferencePaper en_US
dspace.orderedauthors Park, M.; Perrott, M. en


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