Photonic Device Layout Within the Foundry CMOS Design Environment

Author(s)
Orcutt, Jason Scott; Ram, Rajeev J.
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Abstract
A design methodology to layout photonic devices within standard electronic complementary metal-oxide-semiconductor (CMOS) foundry data preparation flows is described. This platform has enabled the fabrication of designs in three foundry scaled-CMOS processes from two semiconductor manufacturers.
Date issued
2010-03
URI
http://hdl.handle.net/1721.1/61756
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Research Laboratory of Electronics
Journal
IEEE Photonics Technology Letters
Publisher
Institute of Electrical and Electronics Engineers
Citation
Orcutt, J.S., and R.J. Ram. “Photonic Device Layout Within the Foundry CMOS Design Environment.” Photonics Technology Letters, IEEE 22.8 (2010): 544-546. © Copyright 2010 IEEE
Version: Final published version
Other identifiers
INSPEC Accession Number: 11180069
ISSN
1041-1135
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