Bias-Stress Effect in Pentacene Organic Thin-Film Transistors
Author(s)Ryu, Kevin K.; Nausieda, Ivan A.; He, David Da; Akinwande, Akintunde Ibitayo; Bulovic, Vladimir; Sodini, Charles G.; ... Show more Show less
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The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage [DELTA]V for a given current. An empirical equation describing [DELTA]V in terms of different gate and drain bias stress measurements and stress times is presented and verified. In the measured devices, [DELTA]V saturates at 14 V, independent of the gate bias-stress condition. A model based on carrier trapping rate equation that accounts for this [DELTA]V saturation is developed. The model suggests that the [DELTA]V saturation is due to the small density of traps compared to the channel carrier density.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology Laboratories
IEEE Transactions on Electron Devices
Institute of Electrical and Electronics Engineers
Ryu, K.K. et al. “Bias-Stress Effect in Pentacene Organic Thin-Film Transistors.” Electron Devices, IEEE Transactions On 57.5 (2010) : 1003-1008. ©2010 IEEE.
Final published version
INSPEC Accession Number: 11256607