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dc.contributor.authordel Alamo, Jesus A.
dc.contributor.authorKim, D.-H.
dc.date.accessioned2012-07-11T15:25:24Z
dc.date.available2012-07-11T15:25:24Z
dc.date.issued2010-04
dc.date.submitted2010-04
dc.identifier.isbn978-1-4244-5065-7
dc.identifier.isbn978-1-4244-5063-3
dc.identifier.issn1930-885X
dc.identifier.otherINSPEC Accession Number: 11501058
dc.identifier.urihttp://hdl.handle.net/1721.1/71580
dc.description.abstractThe increasing difficulties for further scaling down of Si CMOS is bringing to the fore the investigation of alternative channel materials. Among these, III-V compound semiconductors are very attractive due to their outstanding electron transport properties. This paper briefly reviews the prospects and the challenges for a III-V CMOS technology with gate lengths in the 10 nm range.en_US
dc.description.sponsorshipSemiconductor Research Corporationen_US
dc.description.sponsorshipIntel Corporationen_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/VTSA.2010.5488901en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alike 3.0en_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/3.0/en_US
dc.sourcedel Alamo via Amy Stouten_US
dc.titleThe prospects for 10 nm III-V CMOSen_US
dc.typeArticleen_US
dc.identifier.citationdel Alamo, J. A., and D.-H. Kim. “The prospects for 10 nm III-V CMOS.” IEEE, 2010. 166-167.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Microsystems Technology Laboratoriesen_US
dc.contributor.approverdel Alamo, Jesus A.
dc.contributor.mitauthordel Alamo, Jesus A.
dc.contributor.mitauthorKim, D.-H.
dc.relation.journalInternational Symposium on VLSI Technology Systems and Applications (VLSI-TSA), 2010en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
dspace.orderedauthorsdel Alamo, J. A.; Kim, D.-H.en
mit.licenseOPEN_ACCESS_POLICYen_US
mit.metadata.statusComplete


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