ATAC: Improving performance and programmability
Author(s)
Psota, James R.; Miller, Jason E.; Kurian, George; Hoffman, Henry; Beckmann, Nathan Zachary; Eastep, Jonathan Michael; Agarwal, Anant; ... Show more Show less
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Given the current trends in multicore scaling, chips with 1000 cores may exist within the next 5 to 10 years. However, their promise of increased performance will only be reached if their inherent scaling and programming challenges are overcome. Meanwhile, recent advances in nanophotonic device manufacturing are making CMOS-integrated optics a reality-interconnect technology which can provide more bandwidth at lower power than conventional electronics. Perhaps more importantly, optical interconnect also has the potential to enable new, easy-to-use programming models enabled by its inexpensive broadcast mechanism. This paper introduces ATAC, a new manycore architecture that capitalizes on the recent advances in optics to address a number of challenges that future manycore designs will face. The new constraints and opportunities of on-chip optical interconnect are presented and explored in the design of ATAC. Furthermore, this paper discusses ATAC's programming models, and introduces Consumer Tagging, a novel programming model that leverages ATAC's strengths to provide high performance and scalability.
Date issued
2010-08Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Psota, James et al. “ATAC: Improving performance and programmability with on-chip optical networks.” IEEE, 2010. 3325-3328. ©2010 IEEE
Version: Final published version
ISBN
978-1-4244-5308-5
ISSN
978-1-4244-5309-2