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Delay Analysis of Graphene Field-Effect Transistors

dc.contributor.authorWang, Han
dc.contributor.authorHsu, Allen Long
dc.contributor.authorLee, Dong Seup
dc.contributor.authorKim, Ki Kang
dc.contributor.authorKong, Jing
dc.contributor.authorPalacios, Tomas
dc.date.accessioned2012-08-14T19:01:58Z
dc.date.available2012-08-14T19:01:58Z
dc.date.issued2012-02
dc.date.submitted2011-11
dc.identifier.issn0741-3106
dc.identifier.urihttp://hdl.handle.net/1721.1/72126
dc.description.abstractIn this letter, we analyze the carrier transit delay in graphene field-effect transistors (GFETs).The extraction of the intrinsic delay provides a new way to directly estimate carrier velocity from the experimental data, while the breakdown of the total delay into intrinsic, extrinsic, and parasitic components can offer valuable information for optimizing RF GFET structures.en_US
dc.description.sponsorshipUnited States. Office of Naval Research. GATE MURI Projecten_US
dc.description.sponsorshipU.S. Army Research Laboratoryen_US
dc.description.sponsorshipMicroelectronics Advanced Research Corporation (MARCO). MSD Programen_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/led.2011.2180886en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alike 3.0en_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/3.0/en_US
dc.sourcearXiven_US
dc.titleDelay Analysis of Graphene Field-Effect Transistorsen_US
dc.typeArticleen_US
dc.identifier.citationWang, Han et al. “Delay Analysis of Graphene Field-Effect Transistors.” IEEE Electron Device Letters 33.3 (2012): 324–326.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.departmentMassachusetts Institute of Technology. Microsystems Technology Laboratoriesen_US
dc.contributor.departmentMassachusetts Institute of Technology. Research Laboratory of Electronicsen_US
dc.contributor.approverKong, Jing
dc.contributor.mitauthorWang, Han
dc.contributor.mitauthorHsu, Allen Long
dc.contributor.mitauthorLee, Dong Seup
dc.contributor.mitauthorKim, Ki Kang
dc.contributor.mitauthorKong, Jing
dc.contributor.mitauthorPalacios, Tomas
dc.relation.journalIEEE Electron Device Lettersen_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/JournalArticleen_US
eprint.statushttp://purl.org/eprint/status/PeerRevieweden_US
dspace.orderedauthorsWang, Han; Hsu, Allen; Lee, Dong Seup; Kim, Ki Kang; Kong, Jing; Palacios, Tomasen
dc.identifier.orcidhttps://orcid.org/0000-0003-0551-1208
dc.identifier.orcidhttps://orcid.org/0000-0002-2190-563X
dspace.mitauthor.errortrue
mit.licenseOPEN_ACCESS_POLICYen_US
mit.metadata.statusComplete


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