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dc.contributor.authorRamanujam, Rohit Sunkam
dc.contributor.authorSoteriou, Vassos
dc.contributor.authorLin, Bill
dc.contributor.authorPeh, Li-Shiuan
dc.date.accessioned2012-08-30T18:26:36Z
dc.date.available2012-08-30T18:26:36Z
dc.date.issued2010-07
dc.date.submitted2010-05
dc.identifier.isbn978-1-4244-7086-0
dc.identifier.isbn978-1-4244-7085-3
dc.identifier.urihttp://hdl.handle.net/1721.1/72481
dc.description.abstractRouter microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forwarded due to contention. This buffering can be done at the inputs or the outputs of a router, corresponding to an input-buffered router (IBR) or an output-buffered router (OBR). OBRs are attractive because they can sustain higher throughputs and have lower queuing delays under high loads than IBRs. However, a direct implementation of an OBR requires a router speedup equal to the number of ports, making such a design prohibitive under aggressive clocking needs and limited power budgets of most NoC applications. In this paper, we propose a new router design that aims to emulate an OBR practically, based on a distributed shared-buffer (DSB) router architecture. We introduce innovations to address the unique constraints of NoCs, including efficient pipelining and novel flow-control. We also present practical DSB configurations that can reduce the power overhead with negligible degradation in performance. The proposed DSB router achieves up to 19% higher throughput on synthetic traffic and reduces packet latency by 60% on average for SPLASH-2 benchmarks with high contention, compared to a state-of-art pipelined IBR. On average, the saturation throughput of DSB routers is within 10% of the theoretically ideal saturation throughput under the synthetic workloads evaluated.en_US
dc.description.sponsorshipNational Science Foundation (U.S.). (Grant number CCF-0702341)en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/NOCS.2010.17en_US
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en_US
dc.sourceIEEEen_US
dc.titleDesign of a high-throughput distributed shared-buffer NoC routeren_US
dc.typeArticleen_US
dc.identifier.citationRamanujam, Rohit Sunkam et al. “Design of a High-Throughput Distributed Shared-Buffer NoC Router.” Fourth ACM/IEEE International Symposium on Networks-on-Chip 2010 (NOCS). 69–78. © Copyright 2010 IEEEen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverPeh, Li-Shiuan
dc.contributor.mitauthorPeh, Li-Shiuan
dc.relation.journalFourth ACM/IEEE International Symposium on Networks-on-Chip 2010 (NOCS)en_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
dspace.orderedauthorsRamanujam, Rohit Sunkam; Soteriou, Vassos; Lin, Bill; Peh, Li-Shiuanen
dc.identifier.orcidhttps://orcid.org/0000-0001-9010-6519
mit.licensePUBLISHER_POLICYen_US
mit.metadata.statusComplete


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