dc.contributor.author | Dave, Nirav H. | |
dc.contributor.author | Ng, Man Cheuk | |
dc.contributor.author | Pellauer, Michael | |
dc.contributor.author | Mithal, Arvind | |
dc.date.accessioned | 2012-09-17T18:41:49Z | |
dc.date.available | 2012-09-17T18:41:49Z | |
dc.date.issued | 2010-07 | |
dc.identifier.isbn | 978-1-4244-7885-9 | |
dc.identifier.isbn | 978-1-4244-7886-6 | |
dc.identifier.issn | 1936-9492 | |
dc.identifier.other | INSPEC Accession Number: 11499847 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/73018 | |
dc.description.abstract | We propose a practical methodology based on modular refinement to design complex systems. The methodology relies on modules with latency-insensitive interfaces so that the refinements can change the timing contract of a module without affecting the overall functional correctness of the system. Such refinements can exacerbate the unit testing problem for modules whose specifications admit a set of output behaviors for the same input (non-determinism), or modules whose input behavior may be affected by past outputs (feedback). We avoid the difficult problem of generating appropriate unit tests for such modules by using system-level tests as unit tests to verify the correctness of refined modules. We illustrate our methodology by showing how one might develop a microprocessor with an in-order pipeline. We then develop a superscalar pipeline using the in-order pipeline as the starting point. Our methodology leverages the effort of design exploration to reduce the effort of specifying interface contracts and unit testing. | en_US |
dc.description.sponsorship | National Science Foundation (U.S.) (grant CCF- 0541164 on Complex Digital Systems) | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/MEMCOD.2010.5558626 | en_US |
dc.rights | Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. | en_US |
dc.source | IEEE | en_US |
dc.title | A design flow based on modular refinement | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Dave, Nirav et al. “A Design Flow Based on Modular Refinement.” in Proceedings of the 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 26-28 July 2010, Grenoble, Switzerland. IEEE, 2010. 11–20. Web. ©2010 IEEE. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.approver | Mithal, Arvind | |
dc.contributor.mitauthor | Mithal, Arvind | |
dc.contributor.mitauthor | Dave, Nirav H. | |
dc.contributor.mitauthor | Ng, Man Cheuk | |
dc.contributor.mitauthor | Pellauer, Michael | |
dc.relation.journal | Proceedings of the 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010) | en_US |
dc.eprint.version | Final published version | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
dspace.orderedauthors | Dave, Nirav; Ng, Man Cheuk; Pellauer, Michael; Arvind, Michael | en |
dc.identifier.orcid | https://orcid.org/0000-0002-9737-2366 | |
mit.license | PUBLISHER_POLICY | en_US |
mit.metadata.status | Complete | |