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dc.contributor.authorKazior, T. E.
dc.contributor.authorLaRoche, J. R.
dc.contributor.authorUrteaga, M.
dc.contributor.authorBergman, J.
dc.contributor.authorChoe, M. J.
dc.contributor.authorLee, K. J.
dc.contributor.authorSeong, T.
dc.contributor.authorSeo, M.
dc.contributor.authorYen, A.
dc.contributor.authorLubyshev, D.
dc.contributor.authorFastenau, J. M.
dc.contributor.authorLiu, W. K.
dc.contributor.authorSmith, D.
dc.contributor.authorClark, D.
dc.contributor.authorThompson, R.
dc.contributor.authorBulsara, Mayank
dc.contributor.authorFitzgerald, Eugene A.
dc.contributor.authorDrazek, C.
dc.contributor.authorGuiot, E.
dc.date.accessioned2013-10-04T15:49:21Z
dc.date.available2013-10-04T15:49:21Z
dc.date.issued2010-10
dc.identifier.isbn978-1-4244-7437-0
dc.identifier.isbn978-1-4244-7436-3
dc.identifier.otherINSPEC Accession Number: 11630792
dc.identifier.urihttp://hdl.handle.net/1721.1/81316
dc.description.abstractWe present recent results on the direct heterogeneous integration of InP HBTs and Si CMOS on a silicon template wafer or SOLES (Silicon On Lattice Engineered Substrate). InP HBTs whose performance are comparable to HBTs on the native InP substrates have been repeatedly achieved. 100% heterogeneous interconnect yield has been achieved on daisy chain test structures with CMOS-InP HBT spacing (interconnect length) as small as 2.5um. In DARPA COSMOS Phase 1 we designed and fabricated a differential amplifier that met the program Go/NoGo metrics with first pass design success. As the COSMOS Phase 2 demonstration vehicle we designed and fabricated a low power dissipation, high resolution, 500MHz bandwidth digital-to-analog converter (DAC).en_US
dc.description.sponsorshipUnited States. Defense Advanced Research Projects Agency (DARPA COSMOS Program (Contract Number N00014-07-C-0629))en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/CSICS.2010.5619670en_US
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en_US
dc.sourceIEEEen_US
dc.titleHigh Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrateen_US
dc.typeArticleen_US
dc.identifier.citationKazior, T. E., J. R. LaRoche, M. Urteaga, J. Bergman, M. J. Choe, K. J. Lee, T. Seong, et al. “High Performance Mixed Signal Circuits Enabled by the Direct Monolithic Heterogeneous Integration of InP HBT and Si CMOS on a Silicon Substrate.” In 2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Monterey, CA, USA, 3-6 October 2010, 1-4. Institute of Electrical and Electronics Engineers, 2010. © Copyright 2010 IEEE.en_US
dc.contributor.departmentMIT Materials Research Laboratoryen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Materials Science and Engineeringen_US
dc.contributor.mitauthorBulsara, Mayanken_US
dc.contributor.mitauthorFitzgerald, Eugene A.en_US
dc.relation.journal2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)en_US
dc.eprint.versionFinal published versionen_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsKazior, T. E.; LaRoche, J. R.; Urteaga, M.; Bergman, J.; Choe, M. J.; Lee, K. J.; Seong, T.; Seo, M.; Yen, A.; Lubyshev, D.; Fastenau, J. M.; Liu, W. K.; Smith, D.; Clark, D.; Thompson, R.; Bulsara, M. T.; Fitzgerald, E. A.; Drazek, C.; Guiot, E.en_US
dc.identifier.orcidhttps://orcid.org/0000-0002-1891-1959
mit.licensePUBLISHER_POLICYen_US
mit.metadata.statusComplete


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