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dc.contributor.authorKinsy, Michel A.
dc.contributor.authorPellauer, Michael
dc.contributor.authorDevadas, Srinivas
dc.date.accessioned2014-04-14T19:05:42Z
dc.date.available2014-04-14T19:05:42Z
dc.date.issued2013-02
dc.identifier.isbn9781450318877
dc.identifier.urihttp://hdl.handle.net/1721.1/86169
dc.description.abstractThis paper presents Heracles, an open-source, functional, parameterized, synthesizable multicore system toolkit. Such a multi/many-core design platform is a powerful and versatile research and teaching tool for architectural exploration and hardware-software co-design. The Heracles toolkit comprises the soft hardware (HDL) modules, application compiler, and graphical user interface. It is designed with a high degree of modularity to support fast exploration of future multicore processors of di erent topologies, routing schemes, processing elements (cores), and memory system organizations. It is a component-based framework with parameterized interfaces and strong emphasis on module reusability. The compiler toolchain is used to map C or C++ based applications onto the processing units. The GUI allows the user to quickly con gure and launch a system instance for easy factorial development and evaluation. Hardware modules are implemented in synthesizable Verilog and are FPGA platform independent. The Heracles tool is freely available under the open-source MIT license at: http://projects.csail.mit.edu/heraclesen_US
dc.language.isoen_US
dc.publisherAssociation for Computing Machinery (ACM)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1145/2435264.2435287en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alikeen_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/4.0/en_US
dc.sourceMIT web domainen_US
dc.titleHeracles: A Tool for Fast RTL-Based Design Space Exploration of Multicore Processorsen_US
dc.typeArticleen_US
dc.identifier.citationMichel A. Kinsy, Michael Pellauer, and Srinivas Devadas. 2013. Heracles: a tool for fast RTL-based design space exploration of multicore processors. In Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays (FPGA '13). ACM, New York, NY, USA, 125-134.en_US
dc.contributor.departmentLincoln Laboratoryen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.mitauthorKinsy, Michel A.en_US
dc.contributor.mitauthorDevadas, Srinivasen_US
dc.relation.journalProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays (FPGA '13)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
eprint.statushttp://purl.org/eprint/status/NonPeerRevieweden_US
dspace.orderedauthorsKinsy, Michel A.; Pellauer, Michael; Devadas, Srinivasen_US
dc.identifier.orcidhttps://orcid.org/0000-0001-8253-7714
dc.identifier.orcidhttps://orcid.org/0000-0003-4301-1159
mit.licenseOPEN_ACCESS_POLICYen_US
mit.metadata.statusComplete


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