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An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits

Author(s)
Mysore, Omar; Yu, Li; Wei, Lan; Daniel, Luca; Antoniadis, Dimitri A.; Elfadel, Ibrahim M.; Boning, Duane S.; ... Show more Show less
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Abstract
In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.
Date issued
2013-01
URI
http://hdl.handle.net/1721.1/92430
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology Laboratories
Journal
Proceedings of the 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Li Yu, O. Mysore, Lan Wei, L. Daniel, D. Antoniadis, I. Elfadel, and D. Boning. “An Ultra-Compact Virtual Source FET Model for Deeply-Scaled Devices: Parameter Extraction and Validation for Standard Cell Libraries and Digital Circuits.” 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) (January 2013).
Version: Author's final manuscript
ISBN
978-1-4673-3030-5
978-1-4673-3029-9
978-1-4673-3028-2
ISSN
2153-6961

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