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A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration

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dc.contributor.author Chang, Albert H.
dc.contributor.author Lee, Hae-Seung
dc.contributor.author Boning, Duane S.
dc.date.accessioned 2014-12-22T15:52:08Z
dc.date.available 2014-12-22T15:52:08Z
dc.date.issued 2013-09
dc.identifier.isbn 978-1-4799-0645-1
dc.identifier.isbn 978-1-4799-0643-7
dc.identifier.isbn 978-1-4799-0644-4
dc.identifier.issn 1930-8833
dc.identifier.uri http://hdl.handle.net/1721.1/92432
dc.description.abstract A 12-bit 50MS/s SAR ADC implemented in 65nm CMOS technology is presented. The design employs redundancy to relax the DAC settling requirement and to provide sufficient room for errors such that the static nonlinearity caused by capacitor mismatches can be digitally removed. The redundancy is incorporated into the design using a tri-level switching scheme and our modified split-capacitor array to achieve the highest switching efficiency while still preserving the symmetry in error tolerance. A new code-density based digital background calibration algorithm that requires no special calibration signals or additional analog hardware is also developed. The calibration is performed by using the input signal as stimulus and the effectiveness is verified both in simulation and through measured data. The prototype achieves a 67.4dB SNDR at 50MS/s, while dissipating 2.1mW from a 1.2V supply, leading to FoM of 21.9fJ/conv.-step at Nyquist frequency. en_US
dc.description.sponsorship MIT Masdar Program en_US
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers (IEEE) en_US
dc.relation.isversionof http://dx.doi.org/10.1109/ESSCIRC.2013.6649084 en_US
dc.rights Creative Commons Attribution-Noncommercial-Share Alike en_US
dc.rights.uri http://creativecommons.org/licenses/by-nc-sa/4.0/ en_US
dc.source Boning en_US
dc.title A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration en_US
dc.type Article en_US
dc.identifier.citation Chang, Albert H., Hae-Seung Lee, and Duane Boning. “A 12b 50MS/s 2.1mW SAR ADC with Redundancy and Digital Background Calibration.” 2013 Proceedings of the ESSCIRC (ESSCIRC) (September 2013). en_US
dc.contributor.department Massachusetts Institute of Technology. Microsystems Technology Laboratories en_US
dc.contributor.department Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science en_US
dc.contributor.approver Boning, Duane S. en_US
dc.contributor.mitauthor Chang, Albert H. en_US
dc.contributor.mitauthor Lee, Hae-Seung en_US
dc.contributor.mitauthor Boning, Duane S. en_US
dc.relation.journal 2013 Proceedings of the ESSCIRC (ESSCIRC) en_US
dc.identifier.mitlicense OPEN_ACCESS_POLICY en_US
dc.eprint.version Author's final manuscript en_US
dc.type.uri http://purl.org/eprint/type/ConferencePaper en_US
eprint.status http://purl.org/eprint/status/NonPeerReviewed en_US
dspace.orderedauthors Chang, Albert H.; Lee, Hae-Seung; Boning, Duane en_US
dc.identifier.orcid https://orcid.org/0000-0002-7783-0403
dc.identifier.orcid https://orcid.org/0000-0002-0417-445X


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