A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-tier Applications
Author(s)
Chen, Yu-Hsin; Sze, Vivienne
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High Efficiency Video Coding (HEVC) is the latest video coding standard that specifies video resolutions up to 8K Ultra-HD (UHD) at 120 fps to support the next decade of video applications. This results in high-throughput requirements for the context adaptive binary arithmetic coding (CABAC) entropy decoder, which was already a well-known bottleneck in H.264/AVC. To address the throughput challenges, several modifications were made to CABAC during the standardization of HEVC. This work leverages these improvements in the design of a high-throughput HEVC CABAC decoder. It also supports the high-level parallel processing tools introduced by HEVC, including tile and wavefront parallel processing. The proposed design uses a deeply pipelined architecture to achieve a high clock rate. Additional techniques such as the state prefetch logic, latched-based context memory, and separate finite state machines are applied to minimize stall cycles, while multibypass- bin decoding is used to further increase the throughput. The design is implemented in an IBM 45nm SOI process. After place-and-route, its operating frequency reaches 1.6 GHz. The corresponding throughputs achieve up to 1696 and 2314 Mbin/s under common and theoretical worst-case test conditions, respectively. The results show that the design is sufficient to decode in real-time high-tier video bitstreams at level 6.2 (8K UHD at 120 fps), or main-tier bitstreams at level 5.1 (4K UHD at 60 fps) for applications requiring sub-frame latency, such as video conferencing.
Date issued
2014-10Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
IEEE Transactions on Circuits and Systems for Video Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Chen, Yu-Hsin, and Vivienne Sze. “A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications.” IEEE Trans. Circuits Syst. Video Technol. (2014): 1–1.
Version: Author's final manuscript
ISSN
1051-8215
1558-2205