Reconfigurable Processor for Energy-Efficient Computational Photography
Author(s)Rithe, Rahul; Raina, Priyanka; Tenneti, Srikanth V.; Chandrakasan, Anantha P.; Ickes, Nathan J.
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This paper presents an on-chip implementation of a scalable reconfigurable bilateral filtering processor for computational photography applications such as HDR imaging, low-light enhancement, and glare reduction. Careful pipelining and scheduling has minimized the local storage requirement to tens of kB. The 40-nm CMOS test chip operates from 98 MHz at 0.9 V to 25 MHz at 0.5 V. The test chip processes 13 megapixels/s while consuming 17.8 mW at 98 MHz and 0.9 V, achieving significant energy reduction compared with software implementations on recent mobile processors.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology Laboratories
IEEE Journal of Solid-State Circuits
Institute of Electrical and Electronics Engineers (IEEE)
Rithe, Rahul, Priyanka Raina, Nathan Ickes, Srikanth V. Tenneti, and Anantha P. Chandrakasan. “Reconfigurable Processor for Energy-Efficient Computational Photography.” IEEE Journal of Solid-State Circuits 48, no. 11 (November 2013): 2908–2919.
Author's final manuscript