dc.contributor.author | Rithe, Rahul | |
dc.contributor.author | Raina, Priyanka | |
dc.contributor.author | Tenneti, Srikanth V. | |
dc.contributor.author | Chandrakasan, Anantha P. | |
dc.contributor.author | Ickes, Nathan J. | |
dc.date.accessioned | 2015-02-06T16:43:57Z | |
dc.date.available | 2015-02-06T16:43:57Z | |
dc.date.issued | 2013-10 | |
dc.date.submitted | 2013-06 | |
dc.identifier.issn | 0018-9200 | |
dc.identifier.issn | 1558-173X | |
dc.identifier.uri | http://hdl.handle.net/1721.1/93900 | |
dc.description.abstract | This paper presents an on-chip implementation of a scalable reconfigurable bilateral filtering processor for computational photography applications such as HDR imaging, low-light enhancement, and glare reduction. Careful pipelining and scheduling has minimized the local storage requirement to tens of kB. The 40-nm CMOS test chip operates from 98 MHz at 0.9 V to 25 MHz at 0.5 V. The test chip processes 13 megapixels/s while consuming 17.8 mW at 98 MHz and 0.9 V, achieving significant energy reduction compared with software implementations on recent mobile processors. | en_US |
dc.description.sponsorship | Foxconn International Holdings Ltd. | en_US |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/jssc.2013.2282614 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | Chandrakasan | en_US |
dc.title | Reconfigurable Processor for Energy-Efficient Computational Photography | en_US |
dc.type | Article | en_US |
dc.identifier.citation | Rithe, Rahul, Priyanka Raina, Nathan Ickes, Srikanth V. Tenneti, and Anantha P. Chandrakasan. “Reconfigurable Processor for Energy-Efficient Computational Photography.” IEEE Journal of Solid-State Circuits 48, no. 11 (November 2013): 2908–2919. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Microsystems Technology Laboratories | en_US |
dc.contributor.approver | Chandrakasan, Anantha P. | en_US |
dc.contributor.mitauthor | Rithe, Rahul | en_US |
dc.contributor.mitauthor | Raina, Priyanka | en_US |
dc.contributor.mitauthor | Chandrakasan, Anantha P. | en_US |
dc.contributor.mitauthor | Ickes, Nathan J. | en_US |
dc.relation.journal | IEEE Journal of Solid-State Circuits | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/JournalArticle | en_US |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en_US |
dspace.orderedauthors | Rithe, Rahul; Raina, Priyanka; Ickes, Nathan; Tenneti, Srikanth V.; Chandrakasan, Anantha P. | en_US |
dc.identifier.orcid | https://orcid.org/0000-0002-7418-0994 | |
dc.identifier.orcid | https://orcid.org/0000-0002-5977-2748 | |
mit.license | OPEN_ACCESS_POLICY | en_US |
mit.metadata.status | Complete | |