Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS
Author(s)
Nguyen, X.S.; Yadav, S.; Lee, K.H.; Kohen, D.; Kumar, A.; Made, R.I.; Gong, X.; Lee, K.E.; Tan, C.S.; Yoon, S.F.; Chua, S.J.; Fitzgerald, Eugene A; ... Show more Show less
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We report on the growth of In 0.30 Ga 0.70 As channel high-electron mobility transistor (HEMT) epi-layers on a 200 mm silicon wafer by metal organic chemical vapor deposition (MOCVD). The device epi-layers were grown on a silicon substrate by using a ∼ 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded, strain relaxation layer. The achieved epitaxy has a threading dislocation density of (1 - 2) × 10[superscript 7] cm[superscript -2] and a root mean square surface roughness of 6-7 nm. The device active layers include a delta-doped InAlAs bottom barrier, a 15 nm thick InGaAs channel, a 15 nm InGaP top barrier layer and a heavily doped InGaAs contact layer. Long channel MOS-HEMT devices (LG ∼ 20 μm), were fabricated achieving a peak effective electron mobility of ∼ 3700 cm[superscript 2]/V·s.
Date issued
2017-05Department
Massachusetts Institute of Technology. Department of Materials Science and EngineeringJournal
2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference)
Publisher
CS Mantech
Citation
Nguyen, X.S. et al. "Growth of InGaAs-channel transistor layers on large-scale Si wafers for HeteroIntegration with Si CMOS." 2017 International Conference on Compound Semiconductor Manufacturing Technology(2017 CS MANTECH Conference), May 22-25 2017, Indian Wells, California, USA, CS Mantech, May 2017
Version: Author's final manuscript