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Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators
dc.date.accessioned | 2021-11-03T14:10:52Z | |
dc.date.available | 2021-11-03T14:10:52Z | |
dc.date.issued | 2020-12 | |
dc.identifier.uri | https://hdl.handle.net/1721.1/137180 | |
dc.description.abstract | © 2019 IEEE. This paper describes various design considerations for deep neural networks that enable them to operate efficiently and accurately on processing-in-memory accelerators. We highlight important properties of these accelerators and the resulting design considerations using experiments conducted on various state-of-the- art deep neural networks with the large-scale ImageNet dataset. | en_US |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | en_US |
dc.relation.isversionof | 10.1109/IEDM19573.2019.8993662 | en_US |
dc.rights | Creative Commons Attribution-Noncommercial-Share Alike | en_US |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-sa/4.0/ | en_US |
dc.source | arXiv | en_US |
dc.title | Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators | en_US |
dc.type | Article | en_US |
dc.identifier.citation | 2020. "Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators." Technical Digest - International Electron Devices Meeting, IEDM, 2019-December. | |
dc.relation.journal | Technical Digest - International Electron Devices Meeting, IEDM | en_US |
dc.eprint.version | Author's final manuscript | en_US |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en_US |
eprint.status | http://purl.org/eprint/status/NonPeerReviewed | en_US |
dc.date.updated | 2021-04-15T16:58:16Z | |
dspace.orderedauthors | Yang, T-J; Sze, V | en_US |
dspace.date.submission | 2021-04-15T16:58:17Z | |
mit.journal.volume | 2019-December | en_US |
mit.license | OPEN_ACCESS_POLICY | |
mit.metadata.status | Authority Work and Publication Information Needed | en_US |